1. Field
The present disclosure relates to processes for fabricating electronic circuit devices, more particularly, the disclosure relates to a process for assembling three-dimensional systems on a chip and to the structure thus obtained.
2. Description of Related Art
Current methods for wafer-scale integration of different semiconductor technologies typically rely on either heteroepitaxy or wafer bonding techniques. However, both of these techniques are limited in the number of different devices and material systems that can be successfully integrated. Moreover, growth and fabrication procedures optimized for a single device technology often must be compromised to accommodate dissimilar material systems. This forces the costly development of customized processes for every component and prevents the use of low-cost foundries for producing the integrated systems.
In particular, the most basic process for wafer-scale integration is by heteroepitaxy combined with post-growth device processing. However, for the integration of a silicon substrate with group III-V semiconductor materials, components or devices, this process suffers from a large defect density caused by the mismatch in lattice parameters and by the fact that devices in the silicon substrate can only be fabricated through widely-separated “holes” in the epitaxial film. In addition, only one type of III-V layer can be utilized, which means that applications that could benefit from both Gallium Arsenide (GaAs) and Indium Phosphide (InP) devices are not possible.
Somewhat greater flexibility can be achieved through the use of wafer bonding to join silicon and III-V wafers containing already fabricated devices. However, the large thermal expansion mismatch between III-V materials and silicon requires almost complete removal of the III-V substrate prior to interconnect formation or additional processing. A further disadvantage is that wafer bonding techniques can only be used to add a single type of III-V device to silicon. A variant of this approach is to use wafer bonding and layer separation techniques to transfer a thin layer of a III-V material onto an already fabricated silicon integrated circuit wafer that has been overcoated with oxide and planarized. The transferred layer is then processed to form devices and interconnections. However, this approach also suffers from problems due to thermal expansion mismatch as well as thermal degradation of devices present in the silicon substrate during processing of the III-V layer.
For integration at the chip level, there are established methods that rely on surface-mounting techniques for attaching complete die assemblies using solder bumps or wire bonding. The most advanced of these approaches is the “flip-chip” technique that can support the integration of a wide variety of device technologies. However, flip-chip is limited to a two-dimensional planar geometry, resulting in large overall package size. Moreover, this technique is inefficient for the placement of large numbers of components, since placement is performed serially.
Technologies such as Low Temperature Co-fired Ceramics (LTCC) or High-Density Multilayer Interconnect (HDMI) are available for the formation of three-dimensional stacks of passive components. However, these technologies are not usable for three-dimensional integration of active devices. LTCC techniques require sintering at 850° C., which would destroy most processed semiconductor devices. The HDMI technique utilizes multiple levels of flexible polymer films to achieve layer-to-layer interconnects, but does not provide a method for incorporating active devices within a layer. Both LTCC and HDMI are inefficient for the placement of large numbers of components due to their serial nature.
Fluidic self-assembly is one of the latest techniques for mass assembly and integration of pre-fabricated circuits, devices and components from any materials technology onto host circuits. In particular, devices and components are delivered to the host circuits using a fluid transport process. Two different approaches are possible, which differ in the underlying mechanism used to locate, position and connect the components into the larger system. The first approach uses chemically-based driving forces to govern the assembly process like attraction, positioning, orientation, and ordering which are controlled by molecular interactions at the surfaces of the objects. The second approach uses gravitational forces and geometrical constrains like shaped components and complementarily shaped receptacle sites. Both of these approaches have been used to integrate electronic devices into hybrid electronic systems. See, for example, “Self-Assembly of an Operating Electrical Circuit Based on Shape Complementarity and the Hydrophobic Effect,” Advanced Materials, by A. Terfort and G. M. Whitesides, 1998, 10, No. 6, pp. 470-473. A disadvantage of the gravity-based assembly methods is that they are limited to single-layer structures. In fact, since this assembly method involves the filling of receptacle sites on a host substrate by shaped device blocks, it is limited to a two-dimensional assembly. The reason for this limitation is that device blocks must have an unobstructed access to the receptacle sites.
Therefore, there is a need for a process for fabricating highly integrated systems-on-a-chip through the heterogeneous integration of group III-V compound semiconductor devices, RF materials, optical components and sensor elements with microcircuits.